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1. general description the 74LVC1G99 provides a low voltage, ultr a-configurable, multiple function gate with 3-state output. the device can be configured as one of several logic functions including, and, or, nand, nor, xor, xnor, inverter, buffer and mux. no external components are required to configure the device as all inputs can be connected directly to v cc or gnd. the 3-state output is controlled by the output enable input (oe ). a high level at oe causes the output (y) to assume a high-impedance off-state. when oe is low, the output state is determined by the signals applied to the schmitt-trigger inputs (a, b, c and d). due to the use of schm itt-trigger inputs the device is to lerant of slowly changing input signals, transforming them into sharply define d, jitter free output signals. by eliminating leakage current paths to v cc and gnd, the inputs and disabled output are also over-voltage tolerant, making the device suitable for mixed-voltage applications. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventin g the damaging backflow current through the device when it is powered down. the 74LVC1G99 is fully specified over th e supply range from 1.65 v to 5.5 v. 2. features and benefits ? wide supply voltage range from 1.65 v to 5.5 v ? 5 v tolerant inputs for interfacing with 5 v logic ? high noise immunity ? complies with jedec standard: ? jesd8-7 (1.65 v to 1.95 v) ? jesd8-5 (2.3 v to 2.7 v) ? jesd8-b/jesd36 (2.7 v to 3.6 v) ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? 24 ma output drive (v cc =3.0v) ? cmos low power consumption ? latch-up performance exceeds 250 ma ? direct interface with ttl levels ? inputs accept voltages up to 5 v ? multiple package options ? specified from ? 40 cto+85 c and ? 40 c to +125 c. 74LVC1G99 ultra-configurable multiple function gate; 3-state rev. 04 ? 16 april 2010 product data sheet
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 2 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74LVC1G99dp ? 40 c to +125 c tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505-2 74LVC1G99gt ? 40 c to +125 c xson8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 1.95 0.5 mm sot833-1 74LVC1G99gf ? 40 c to +125 c xson8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1 0.5 mm sot1089 74LVC1G99gd ? 40 c to +125 c xson8u plastic extremely thin small outline package; no leads; 8 terminals; utlp based; body 3 2 0.5 mm sot996-2 74LVC1G99gm ? 40 c to +125 c xqfn8u plastic extremely thin quad flat package; no leads; 8 terminals; utlp based; body 1.6 1.6 0.5 mm sot902-1 table 2. marking codes [1] type number marking code 74LVC1G99dp v99 74LVC1G99gt v99 74LVC1G99gf yf 74LVC1G99gd v99 74LVC1G99gm v99 fig 1. logic symbol 001aah32 2 oe a b y c d
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 3 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 6. pinning information 6.1 pinning fig 2. pin configuration sot505-2 (tssop8) fi g 3. pin configuration sot833-1 and sot1089 (xson8) 74LVC1G99 oe v cc ay bd gnd c 001aah323 1 2 3 4 6 5 8 7 74LVC1G99 d y v cc c b a oe gnd 001aah324 36 27 18 45 transparent top view fig 4. pin configuration sot996-2 (xson8u) fi g 5. pin configuration sot902-1 (xqfn8u) 001aal775 74LVC1G99 transparent top view 8 7 6 5 1 2 3 4 oe a b gnd v cc y d c 001aah32 5 a d oe v cc b y gnd c transparent top view 3 6 4 1 5 8 7 2 terminal 1 index area 74LVC1G99
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 4 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. table 3. pin description symbol pin description sot505-2, sot833-1, sot996-2 and sot1089 sot902-1 oe 1 7 output enable input oe (active low) a 2 6 data input b 3 5 data input gnd 4 4 ground (0 v) c 5 3 data input d 6 2 data input y 7 1 data output v cc 8 8 supply voltage table 4. function table [1] input output oe d c b a y llllll llllhh lllhll lllhhh llhlll llhlhl l l hhl h l l hhhh lhlllh lhllhl lhlhlh lhlhhl lhhllh l hhl hh l hhhl l l hhhhl hxxxxz
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 5 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 7.1 logic configurations 7.2 3-state buffer functions available [1] h = high voltage level; l = low voltage level. table 5. function selection table primary function complementary function 3-state buffer 3-state inverter 3-state 2-input multiplexer 3-state 2-input multiplexer with inverting output 3-state 2-input and 3-state 2-input nor with two inverting inputs 3-state 2-input and with one inverting input 3 -state 2-input nor with one inverting input 3-state 2-input and with two inverting inputs 3-state 2-input nor 3-state 2-input nand 3-state 2-i nput or with two inverting inputs 3-state 2-input nand with one inverting input 3 -state 2-input or with one inverting input 3-state 2-input nand with two inve rting inputs 3-state 2-input or 3-state 2-input xor 3-state 2-input xnor 3-state 2-i nput xor with one inverting input table 6. function table [1] see figure 6 . function input oe a b c d 3-state buffer l input h or l l l l h or l input h l llhinputl lhlinputh l h h or l l input l h or l l h input lllh or linput fig 6. 3-state buffer function 001aah32 6 oe input y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 6 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 7.3 3-state inverter functions available [1] h = high voltage level; l = low voltage level. x = don?t care. 7.4 3-state multiplexer functions available [1] h = high voltage level; l = low voltage level. table 7. function table [1] see figure 7 . function input oe a b c d 3-state inverter l input h or l l h l x input h h llhinputh lhlinputl l h h or l l input l h or l h h input l h h h or l input fig 7. 3-state inverter function 001aah32 7 oe input y table 8. function table [1] see figure 8 . function input oe a b c d 3-state 2-input multiplexer l input 1 input 2 input 1 or input 2 l l input 2 input 1 input 2 or input 1 l l input 1 input 2 input 1 or input 2 h l input 2 input 1 input 2 or input 1 h fig 8. 3-state 2-input multiplexer function oe input 1 input 2 a/b y oe input 1 001aah32 8 input 2 a/b y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 7 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 7.5 3-state and/nor functions available [1] h = high voltage level; l = low voltage level. [1] h = high voltage level; l = low voltage level. table 9. function table [1] see figure 9 . number of inputs function input and/nand or/nor oe a b c d 2 3-state and 3-state nor l l input 1 input 2 l 2 3-state and 3-state nor l l input 2 input 1 l fig 9. 3-state and/nor function 001aah32 9 oe input 1 input 2 y oe input 1 input 2 y table 10. function table [1] see figure 10 . number of inputs function input and/nand or/nor oe a b c d 2 3-state and 3-state nor l input 2 l input 1 l 2 3-state and 3-state nor l h input 1 input 2 h fig 10. 3-state and/nor function 001aah33 0 oe input 1 input 2 y oe input 1 input 2 y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 8 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state [1] h = high voltage level; l = low voltage level. [1] h = high voltage level; l = low voltage level. table 11. function table [1] see figure 11 . number of inputs function input and/nand or/nor oe a b c d 2 3-state and 3-state nor l input 1 l input 2 l 2 3-state and 3-state nor l h input 2 input 1 h fig 11. 3-state and/nor function 001aah33 1 oe input 1 input 2 y oe input 1 input 2 y table 12. function table [1] see figure 12 . number of inputs function input and/nand or/nor oe a b c d 2 3-state and 3-state nor l input 1 h input 2 l 2 3-state and 3-state nor l input 2 h input 1 l fig 12. 3-state and/nor function 001aah33 2 oe input 1 input 2 y oe input 1 input 2 y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 9 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 7.6 3-state nand/or functions available [1] h = high voltage level; l = low voltage level. [1] h = high voltage level; l = low voltage level. table 13. function table [1] see figure 13 . number of inputs function input and/nand or/nor oe a b c d 2 3-state nand 3-state or l l input 1 input 2 h 2 3-state nand 3-state or l l input 2 input 1 h fig 13. 3-state nand/or function 001aah33 3 oe input 1 input 2 y oe input 1 input 2 y table 14. function table [1] see figure 14 . number of inputs function input and/nand or/nor oe a b c d 2 3-state nand 3-state or l input 2 l input 1 h 2 3-state nand 3-state or l h input 1 input 2 l fig 14. 3-state nand/or function 001aah33 4 oe input 1 input 2 y oe input 1 input 2 y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 10 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state [1] h = high voltage level; l = low voltage level. [1] h = high voltage level; l = low voltage level. table 15. function table [1] see figure 15 . number of inputs function input and/nand or/nor oe a b c d 2 3-state nand 3-state or l input 1 l input 2 h 2 3-state nand 3-state or l h input 2 input 1 l fig 15. 3-state and/nor function 001aah33 5 oe input 1 input 2 y oe input 1 input 2 y table 16. function table [1] see figure 16 . number of inputs function input and/nand or/nor oe a b c d 2 3-state nand 3-state or l input 1 h input 2 l 2 3-state nand 3-state or l input 2 h input 1 l fig 16. 3-state and/nor function 001aah33 6 oe input 1 input 2 y oe input 1 input 2 y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 11 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 7.7 3-state xor/xnor functions available [1] h = high voltage level; l = low voltage level. [1] h = high voltage level; l = low voltage level. table 17. function table [1] see figure 17 . function input oe a b c d 3-state xor l input 1 h or l l input 2 l input 2 h or l l input 1 l h or l input 1 h input 2 l h or l input 2 h input 1 l l h input 1 input 2 l l h input 2 input 1 fig 17. 3-state xor function 001aah33 7 oe input 1 input 2 y table 18. function table [1] see figure 18 . function input oe a b c d 3-state xor l h l input 1 input 2 fig 18. 3-state xor function 001aah33 8 oe input 1 input 2 y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 12 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state [1] h = high voltage level; l = low voltage level. [1] h = high voltage level; l = low voltage level. table 19. function table [1] see figure 19 . function input oe a b c d 3-state xor l h l input 1 input 2 fig 19. 3-state xor function 001aah33 9 oe input 1 input 2 y table 20. function table [1] see figure 20 . function input oe a b c d 3-state xnor l h l input 1 input 2 l h l input 2 input 1 fig 20. 3-state xnor function 001aah34 0 oe input 1 input 2 y
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 13 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 8. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] when v cc = 0 v (power-down mode), the output voltage can be 5.5 v in normal operation. [3] for tssop8 package: above 110 c the value of p tot derates linearly with 8.0 mw/k. for xson8, xson8u and xqfn8u packages: above 118 c the value of p tot derates linearly with 7.8 mw/k. 9. recommended operating conditions table 21. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v i ik input clamping current v i < 0 v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o > v cc or v o < 0 v - 50 ma v o output voltage active mode [1] [2] ? 0.5 v cc + 0.5 v power-down mode [1] [2] ? 0.5 +6.5 v i o output current v o = 0 v to v cc - 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma p tot total power dissipation t amb = ? 40 c to +125 c [3] - 250 mw t stg storage temperature ? 65 +150 c table 22. operating conditions symbol parameter conditions min max unit v cc supply voltage 1.65 5.5 v v i input voltage 0 5.5 v v o output voltage active mode 0 v cc v power-down mode; v cc =0v 0 5.5 v t amb ambient temperature ? 40 +125 c t/ v input transition rise and fall rate v cc = 1.65 v to 2.7 v - 20 ns/v v cc = 2.7 v to 4.5 v - 10 ns/v v cc = 4.5 v to 5.5 v - 5 ns/v
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 14 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 10. static characteristics table 23. static characteristics at recommended operating conditions. vo ltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit t amb = ? 40 c to +85 c v oh high-level output voltage v i =v t+ or v t ? i o = ? 100 a; v cc = 1.65 v to 5.5 v v cc ? 0.1 - - v i o = ? 4ma; v cc = 1.65 v 1.2 - - v i o = ? 8ma; v cc = 2.3 v 1.9 - - v i o = ? 12 ma; v cc = 2.7 v 2.2 - - v i o = ? 24 ma; v cc = 3.0 v 2.3 - - v i o = ? 32 ma; v cc = 4.5 v 3.8 - - v v ol low-level output voltage v i =v t+ or v t ? i o =100 a; v cc = 1.65 v to 5.5 v - - 0.1 v i o =4ma; v cc = 1.65 v - - 0.45 v i o =8ma; v cc = 2.3 v - - 0.3 v i o =12ma; v cc = 2.7 v - - 0.4 v i o =24ma; v cc = 3.0 v - - 0.55 v i o =32ma; v cc = 4.5 v - - 0.55 v i i input leakage current v cc = 0 v to 5.5 v; v i =5.5vorgnd - 0.1 5 a i oz off-state output current v cc = 3.6 v; v i = v ih or v il ; v o = 5.5 v or gnd - 0.1 10 a i off power-off leakage current v cc = 0 v; v i or v o =5.5v - 0.1 10 a i cc supply current v cc = 1.65 v to 5.5 v; v i = 5.5 v or gnd; i o =0a -0.110 a i cc additional supply current per pin; v cc = 2.3 v to 5.5 v; v i =v cc ? 0.6 v; i o =0 a -5500 a c i input capacitance v cc = 3.3 v; v i = gnd to v cc -2.5-pf t amb = ? 40 c to +125 c v oh high-level output voltage v i =v t+ or v t ? i o = ? 100 a; v cc = 1.65 v to 5.5 v v cc ? 0.1 - - v i o = ? 4ma; v cc = 1.65 v 0.95 - - v i o = ? 8ma; v cc = 2.3 v 1.7 - - v i o = ? 12 ma; v cc = 2.7 v 1.9 - - v i o = ? 24 ma; v cc = 3.0 v 2.0 - - v i o = ? 32 ma; v cc = 4.5 v 3.4 - - v v ol low-level output voltage v i =v t+ or v t ? i o =100 a; v cc = 1.65 v to 5.5 v - - 0.1 v i o =4ma; v cc = 1.65 v - - 0.70 v i o =8ma; v cc = 2.3 v - - 0.45 v i o =12ma; v cc = 2.7 v - - 0.60 v i o =24ma; v cc = 3.0 v - - 0.80 v i o =32ma; v cc = 4.5 v - - 0.80 v
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 15 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state [1] all typical values are measured at v cc = 3.3 v and t amb =25 c. 11. dynamic characteristics i i input leakage current v cc = 0 v to 5.5 v; v i =5.5vorgnd - - 100 a i oz off-state output current v cc = 3.6 v; v i = v ih or v il ; v o = 5.5 v or gnd -- 200 a i off power-off leakage current v cc = 0 v; v i or v o =5.5v - - 200 a i cc supply current v cc = 1.65 v to 5.5 v; v i = 5.5 v or gnd; i o =0a --200 a i cc additional supply current per pin; v cc = 2.3 v to 5.5 v; v i =v cc ? 0.6 v; i o =0 a - - 5000 a table 23. static characteristics ?continued at recommended operating conditions. vo ltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit table 24. dynamic characteristics voltages are referenced to gnd (ground = 0 v; for test circuit see figure 23 . symbol parameter conditions 25 c ? 40 c to +125 c unit min typ [1] max min max (85 c) max (125 c) t pd propagation delay a to y; see figure 21 [2] v cc = 1.65 v to 1.95 v - 7.5 - 2.8 30.8 38.5 ns v cc = 2.3 v to 2.7 v - 5.0 - 2.0 11.7 14.6 ns v cc = 2.7 v - 5.4 - 2.0 9.0 11.3 ns v cc = 3.0 v to 3.6 v - 4.5 - 1.8 8.4 10.5 ns v cc = 4.5 v to 5.5 v - 3.8 - 1.8 5.5 6.9 ns b to y; see figure 21 [2] v cc = 1.65 v to 1.95 v - 7.5 - 2.8 28.9 36.2 ns v cc = 2.3 v to 2.7 v - 5.0 - 2.0 11.3 14.2 ns v cc = 2.7 v - 5.4 - 2.0 9.0 11.3 ns v cc = 3.0 v to 3.6 v - 4.5 - 1.8 8.2 10.3 ns v cc = 4.5 v to 5.5 v - 3.8 - 1.8 5.4 6.8 ns c to y; see figure 21 [2] v cc = 1.65 v to 1.95 v - 7.8 - 3.2 29.8 37.3 ns v cc = 2.3 v to 2.7 v - 5.2 - 2.3 12.3 15.4 ns v cc = 2.7 v - 5.3 - 2.3 9.6 12.0 ns v cc = 3.0 v to 3.6 v - 4.6 - 2.3 8.6 10.8 ns v cc = 4.5 v to 5.5 v - 3.8 - 1.8 5.7 7.2 ns d to y; see figure 21 [2] v cc = 1.65 v to 1.95 v - 7.0 - 2.8 25.7 32.2 ns v cc = 2.3 v to 2.7 v - 4.6 - 2.0 10.7 13.4 ns v cc = 2.7 v - 4.8 - 2.0 9.2 11.5 ns v cc = 3.0 v to 3.6 v - 4.1 - 1.8 7.6 9.5 ns v cc = 4.5 v to 5.5 v - 3.4 - 1.6 5.2 6.5 ns
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 16 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state [1] all typical values are measured at nominal v cc . [2] t pd is the same as t plh and t phl . [3] t en is the same as t pzh and t pzl . [4] t dis is the same as t phz and t plz . [5] c pd is used to determine the dynamic power dissipation (p d in w). p d =c pd v cc 2 f i n+ (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; (c l v cc 2 f o ) = sum of the outputs. t en enable time oe to y; see figure 22 [3] v cc = 1.65 v to 1.95 v - 5.7 - 2.0 25.2 32.0 ns v cc = 2.3 v to 2.7 v - 3.8 - 1.4 11.3 14.0 ns v cc = 2.7 v - 4.2 - 1.4 8.6 11.0 ns v cc = 3.0 v to 3.6 v - 3.5 - 1.4 7.0 9.0 ns v cc = 4.5 v to 5.5 v - 2.7 - 1.4 4.7 6.0 ns t dis disable time oe to y; see figure 22 [4] v cc = 1.65 v to 1.95 v - 5.7 - 3.0 15.0 19.0 ns v cc = 2.3 v to 2.7 v - 3.6 - 2.0 5.8 7.3 ns v cc = 2.7 v - 4.5 - 2.0 6.6 8.2 ns v cc = 3.0 v to 3.6 v - 4.5 - 2.1 5.9 7.4 ns v cc = 4.5 v to 5.5 v - 3.4 - 1.0 4.5 5.6 ns c pd power dissipation capacitance per buffer (output enabled); f i = 10 mhz; c l = 50 pf; v i = gnd to v cc [5] v cc = 1.65 v to 1.95 v - 14 - - - - pf v cc = 2.3 v to 2.7 v - 16 - - - - pf v cc = 2.7 v - 18 - - - - pf v cc = 3.0 v to 3.6 v - 25 - - - - pf v cc = 4.5 v to 5.5 v - 30 - - - - pf table 24. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v; for test circuit see figure 23 . symbol parameter conditions 25 c ? 40 c to +125 c unit min typ [1] max min max (85 c) max (125 c)
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 17 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 12. waveforms measurement points are given in table 25 . logic levels: v ol and v oh are typical output voltage drop that occur with the output load. fig 21. the data input (a, b, c, d) to output (y) propagation delays 001aah34 1 t plh t phl t phl v m v m v m v m v m v i gnd a, b, c, d input y output y output v oh v ol v oh v ol v m t plh measurement points are given in table 25 . logic levels: v ol and v oh are typical output voltage drop that occur with the output load. fig 22. 3-state enable and disable times mna64 4 t plz t phz outputs disabled outputs enabled v y v x outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v ol v oh v cc v m gnd gnd t pzl t pzh v m v m table 25. measurement points supply voltage input output v cc v m v m v x v y 1.65 v to 1.95 v 0.5v cc 0.5v cc v ol + 0.15 v v oh ? 0.15 v 2.3 v to 2.7 v 0.5v cc 0.5v cc v ol + 0.15 v v oh ? 0.15 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 3.0 v to 3.6 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 4.5 v to 5.5 v 0.5v cc 0.5v cc v ol + 0.3 v v oh ? 0.3 v
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 18 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 13. transfer characteristics test data is given in table 26 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 23. load circuitry for switching times v ext v cc v i v o mna61 6 dut c l r t r l r l g table 26. test data supply voltage input load v ext v i t r = t f c l r l t plh , t phl t pzh , t phz t pzl , t plz 1.65 v to 1.95 v v cc 2.0 ns 30 pf 1 k open gnd 2v cc 2.3 v to 2.7 v v cc 2.0 ns 30 pf 500 open gnd 2v cc 2.7 v 2.7 v 2.5 ns 50 pf 500 open gnd 6 v 3.0 v to 3.6 v 2.7 v 2.5 ns 50 pf 500 open gnd 6 v 4.5 v to 5.5 v v cc 2.5 ns 50 pf 500 open gnd 2v cc table 27. transfer characteristics voltages are referenced to gnd (ground = 0 v; for test circuit see figure 23 symbol parameter conditions ? 40 c to +85 c ? 40 c to +125 c unit min typ [1] max min max v t+ positive-going threshold voltage see figure 24 , figure 25 , figure 26 , figure 27 and figure 28 v cc = 1.8 v 0.70 1.02 1.20 0.67 1.20 v v cc = 2.3 v 1.11 1.42 1.60 1.08 1.60 v v cc = 3.0 v 1.50 1.79 2.00 1.47 2.00 v v cc = 4.5 v 2.16 2.52 2.74 2.13 2.74 v v cc = 5.5 v 2.61 2.99 3.33 2.58 3.33 v
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 19 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state [1] all typical values are measured at t amb = 25 c 14. waveforms trans fer characteristics v t ? negative-going threshold voltage see figure 24 , figure 25 , figure 26 , figure 27 and figure 28 v cc = 1.8 v 0.30 0.53 0.72 0.30 0.75 v v cc = 2.3 v 0.58 0.77 1.00 0.58 1.03 v v cc = 3.0 v 0.80 1.04 1.30 0.80 1.33 v v cc = 4.5 v 1.21 1.55 1.90 1.21 1.93 v v cc = 5.5 v 1.45 1.86 2.29 1.45 2.32 v v h hysteresis voltage (v t+ ? v t ? ); see figure 24 , figure 25 , figure 26 , figure 27 and figure 28 v cc = 1.8 v 0.30 0.48 0.62 0.23 0.62 v v cc = 2.3 v 0.40 0.64 0.80 0.34 0.80 v v cc = 3.0 v 0.50 0.75 1.00 0.44 1.00 v v cc = 4.5 v 0.71 0.97 1.20 0.65 1.20 v v cc = 5.5 v 0.71 1.13 1.40 0.65 1.40 v table 27. transfer characteristics ?continued voltages are referenced to gnd (ground = 0 v; for test circuit see figure 23 symbol parameter conditions ? 40 c to +85 c ? 40 c to +125 c unit min typ [1] max min max fig 24. transfer characteristic fig 25. definition of v t+ , v t ? and v h mna20 7 v o v i v h v t+ v t ? mna208 v o v i v h v t+ v t ?
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 20 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state fig 26. transfer characteristic fig 27. definition of v t+ , v t ? and v h mnb15 4 v o v h v i v t+ v t ? mnb15 5 v o v i v h v t+ v t ? fig 28. typical 74LVC1G99 transfer characteristic; v cc =3.0v 001aab594 v i (v) 03 2 1 8 4 12 16 i cc (ma) 0
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 21 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 15. package outline fig 29. package outline sot505-2 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (1) z (1) references outline version european projection issue date iec jedec jeita mm 0.15 0.00 0.95 0.75 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.70 0.35 8 0 0.13 0.1 0.2 0.5 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.47 0.33 sot505-2 - - - 02-01-16 w m b p d z e 0.25 14 8 5 a 2 a 1 l p (a 3 ) detail x a l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505- 2 1.1 pin 1 index
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 22 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state fig 30. package outline sot833-1 (xson8) terminal 1 index area references outline version european projection issue date iec jedec jeita sot833-1 - - - mo-252 - - - sot833- 1 07-11-14 07-12-07 dimensions (mm are the original dimensions) xson8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 2.0 1.9 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.5 0.6 a (1) max 0.5 0.04 1 8 2 7 3 6 4 5 8 (2) 4 (2) a
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 23 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state fig 31. package outline sot1089 (xson8) references outline version european projection issue date iec jedec jeita sot1089 mo-252 sot1089_po 10-04-09 10-04-12 unit mm max nom min 0.5 0.04 1.40 1.35 1.30 1.05 1.00 0.95 0.55 0.35 0.35 0.30 0.27 a (1) dimensions note 1. including plating thickness. 2. visible depending upon used manufacturing technology. x son8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm sot108 9 a 1 bl 1 0.40 0.35 0.32 0.20 0.15 0.12 deee 1 l 0 0.5 1 mm scale terminal 1 index area e d detail x a a 1 l l 1 b e 1 e terminal 1 index area 1 4 8 5 (4 ) (2) (8 ) (2) x
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 24 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state fig 32. package outline sot996-2 (xson8u) references outline version european projection issue date iec jedec jeita sot996-2 - - - - - - sot996- 2 07-12-18 07-12-21 unit a max mm 0.5 0.05 0.00 0.35 0.15 3.1 2.9 0.5 1.5 0.5 0.3 0.6 0.4 0.1 0.05 a 1 dimensions (mm are the original dimensions) x son8u: plastic extremely thin small outline package; no leads; 8 terminals; utlp based; body 3 x 2 x 0.5 mm 0 1 2 mm scale b d 2.1 1.9 e e e 1 l l 1 0.15 0.05 l 2 v w 0.05 y y 1 0.1 c y c y 1 x b 14 85 e 1 e a c b v m c w m l 2 l 1 l terminal 1 index area b a d e detail x a a 1
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 25 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state fig 33. package outline sot902-1 (xqfn8u) references outline version european projection issue date iec jedec jeita sot902-1 mo-255 - - - - - - sot902- 1 05-11-25 07-11-14 unit a max mm 0.5 a 1 0.25 0.15 0.05 0.00 1.65 1.55 0.35 0.25 0.15 0.05 dimensions (mm are the original dimensions) x qfn8u: plastic extremely thin quad flat package; no leads; 8 terminals; utlp based; body 1.6 x 1.6 x 0.5 mm b dl e 1 1.65 1.55 e e l 1 v 0.1 0.55 0.5 w 0.05 y 0.05 0.05 y 1 0 1 2 mm scale x c y c y 1 terminal 1 index area terminal 1 index area b a d e detail x a a 1 b 8 7 6 5 e 1 e 1 e e a c b ? v m c ? w m 4 1 2 3 l l 1 metal area not for soldering
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 26 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 16. abbreviations 17. revision history table 28. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 29. revision history document id release date data sheet status change notice supersedes 74LVC1G99_4 20100416 product data sheet - 74LVC1G99_3 modifications: ? added type number 74LVC1G99gd (xson8u package) 74LVC1G99_3 20091203 product data sheet - 74LVC1G99_2 74LVC1G99_2 20080208 product data sheet - 74LVC1G99_1 74LVC1G99_1 20080103 product data sheet - -
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 27 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
74LVC1G99_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 16 april 2010 28 of 29 nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74LVC1G99 ultra-configurable multiple function gate; 3-state ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 april 2010 document identifier: 74LVC1G99_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 logic configurations . . . . . . . . . . . . . . . . . . . . . 5 7.2 3-state buffer functions available . . . . . . . . . . . 5 7.3 3-state inverter functions available . . . . . . . . . . 6 7.4 3-state multiplexer functions available . . . . . . . 6 7.5 3-state and/nor functions available. . . . . . . . 7 7.6 3-state nand/or functions available. . . . . . . . 9 7.7 3-state xor/xnor functions available . . . . . 11 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 9 recommended operating conditions. . . . . . . 13 10 static characteristics. . . . . . . . . . . . . . . . . . . . 14 11 dynamic characteristics . . . . . . . . . . . . . . . . . 15 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 transfer characteristics . . . . . . . . . . . . . . . . . 18 14 waveforms transfer characteristics. . . . . . . . 19 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 27 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 19 contact information. . . . . . . . . . . . . . . . . . . . . 28 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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